1. Technical Field
The present invention relates to a transfer circuit, a transmitter, a receiver and a test apparatus.
2. Related Art
A known test apparatus tests a device under test such as a semiconductor circuit by measuring a signal under measurement that is output from the device under test and judging whether the device under test is acceptable based on the result of the measurement. Such a test apparatus uses a comparator to compare the signal level of the signal under measurement against a predetermined threshold value in order to convert the waveform of the signal under measurement into a binary waveform. The test apparatus then uses a CMOS circuit, which forms the following stage, to measure the binary waveform in order to judge whether the device under test is acceptable.
Required to receive the signal under measurement from the device under test, the comparator used in the test apparatus preferably operates at high speed and allows a wide range of input voltages. Therefore, the IC of the comparator is fabricated by utilizing high-mobility semiconductor fabrication technologies with the use of bipolar junction transistors and compound semiconductors.
On the other hand, the circuit of the following stage after the comparator preferably operates at high speed, is highly integrated, and saves power. Therefore, the circuit of the following stage is fabricated by using CMOS processes. The CMOS circuit of the following stage attains the above-mentioned desirable characteristics through miniaturization and a lower power supply voltage.
As the device under test such as a semiconductor circuit operates at an increasingly high frequency, the interface of the CMOS circuit is required to operate at a data rate of several Gbps to 10 Gbps or higher. To satisfy this requirement, the interface of the CMOS circuit is formed by using a low-voltage differential signal circuit (LVDS), a current mode logic circuit (CML), or the like, and often has cascade-connected transistors of four or more stages. Here, the CMOS circuit, which has a lowered power supply voltage, disadvantageously has design difficulties and lowered input/output levels.
In particular, many ultrahigh-speed interfaces formed by using the CMOS processes that achieve miniaturization of 90 nm or less may correctly operate when the input common-mode voltage ranges from approximately 200 mV to 300 mV. Thus, the voltage of the signal received at the interface of the CMOS circuit may not satisfy the input common-mode voltage due to the offset error of the power supply voltage, the waveform degradation resulting from the loss during the transfer line, and other factors. This drawback will become more serious as CMOS devices become further miniaturized in the future.
To solve this issue, a general transfer circuit may conventionally use the AC coupling scheme. In a transfer circuit employing the AC coupling scheme, a signal to be transferred is encoded by a transmitter and then transferred to a receiver via an AC coupled capacitor. The receiver applies a desired bias to the signal that has passed through the AC coupled capacitor, thereby inputting a signal having an ideal common level (bias level) to the circuit of the following stage.
The following patent document is a related prior art document.
Patent Document 1: Japanese Patent Application Publication No. 10-322143
There are, however, difficulties in utilizing the above-mentioned AC coupling scheme for the transfer circuit between the comparator IC and the CMOS circuit in the test apparatus that is designed to test the device under test such as a semiconductor circuit to transfer signals, for the following reason. In the test apparatus, the signal under measurement is transferred in the state of maintaining timing information therein to the CMOS circuit so that the CMOS circuit can measure the waveform, the logic pattern and the like of the signal under measurement. When the AC coupling scheme is used, however, the timing information of the signal under measurement is lost since the signal under measurement is encoded and then transferred to the CMOS circuit. Furthermore, the signal under measurement output from the device under test may be a DC signal. In such cases, the AC coupling scheme cannot be used to measure the DC signal.
In light of the above, it is desired to realize a transfer circuit for use in a test apparatus and the like that can input into a circuit of the following stage a signal having a predetermined common level without the use of the AC coupling scheme. Here, note that the common level of the signal transferred through the transfer circuit may vary in accordance with the variation in temperature, power supply voltage, and other parameters. Therefore, it is also desired to control the common level so as to satisfy the input common-mode voltage even when the temperature, the power supply voltage and other parameters vary.